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cy7c1049dv33 4-mbit (512 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05475 rev. *h revised november 16, 2011 4-mbit (512 k 8) static ram features pin and function compatible with cy7c1049cv33 high speed ? t aa = 10 ns low active power ? i cc = 90 ma at 10 ns low cmos standby power ? i sb2 = 10 ma 2.0 v data retention automatic power down when deselected ttl compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 36-pin (400 mil) molded soj and 44-pin tsop ii packages functional description the cy7c1049dv33 is a high per formance cmos static ram organized as 512k words by 8-bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tristate drivers. you can write to the device by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (io 0 through io 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). you can read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pi ns appear on the i/o pins. the eight input or output pins (io 0 through io 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049dv33 is available in standard 400 mil wide 36 -pin soj package and 44-pin tsop ii package with center power and ground (revolutionary) pinout. logic block diagram a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down ce we oe row decoder column decoder 512k x 8 array input buffer a 10 a 13 a 14 a 15 a 16 a 17 a 11 a 12 a 18
cy7c1049dv33 document number: 38-05475 rev. *h page 2 of 14 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 4 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 ac switching characteristics ......................................... 6 switching waveforms ...................................................... 7 truth table ........................................................................ 9 ordering information ........................................................ 9 ordering code definitions ..... ...................................... 9 package diagrams .......................................................... 10 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14
cy7c1049dv33 document number: 38-05475 rev. *h page 3 of 14 pin configuration selection guide description -10 (industrial) unit maximum access time 10 ns maximum operating current 90 ma maximum cmos standby current 10 ma 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 nc 18 17 20 19 27 28 25 26 22 21 23 24 44-pin tsop ii top view nc nc nc nc a 0 a 1 a 2 a 8 a 7 a 11 a 10 nc nc nc a 9 nc nc a 18 a 17 a 16 a 3 a 6 a 4 ce io 0 io 1 io 2 io 3 we a 5 a 13 a 14 io 4 io 5 io 6 io 7 oe a 15 v cc v cc v ss v ss a 12 10 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 12 13 16 15 29 30 18 17 20 19 27 28 25 26 22 21 23 24 36-pin soj top view nc a 0 a 1 a 2 a 8 a 7 a 11 a 10 nc a 9 a 18 a 17 a 16 a 3 a 6 a 4 ce io 0 io 1 io 2 io 3 we a 5 a 13 a 14 io 4 io 5 io 6 io 7 oe a 15 v cc v cc gnd gnd a 12 10
cy7c1049dv33 document number: 38-05475 rev. *h page 4 of 14 maximum ratings exceeding the maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ..... ............ ............... ?65 c to +150 c ambient temperature with power applied .... .............. .............. .......... ?55 c to +125 c supply voltage on v cc to relative gnd [1] .................................?0.3 v to +4.6 v dc voltage applied to outputs in high z state [1] ................................. ?0.3 v to v cc + 0.3 v dc input voltage [1] .............................. ?0.3 v to v cc + 0.3 v current into outputs (low) ........................................ 20 ma static discharge voltage .......................................... > 2001 v (mil-std-883, method 3015) latch up current ..................................................... > 200 ma operating range range ambient temperature v cc speed industrial ?40 c to +85 c 3.3 v 0.3 v 10 ns electrical characteristics over the operating range parameter description test conditions -10 (industrial) unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih [1] input high voltage 2.0 v cc + 0.3 v v il [1] input low voltage [1] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max, f = f max = 1/t rc 100 mhz ? 90 ma 83 mhz ? 80 ma 66 mhz ? 70 ma 40 mhz ? 60 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih ; v in > v ih or v in < v il , f = f max ?20ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?10ma capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 8pf note 1. v il (min.) = ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 20 ns.
cy7c1049dv33 document number: 38-05475 rev. *h page 5 of 14 thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 36-pin soj package 44-pin tsop ii package unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two layer printed circuit board 57.91 50.66 c/w jc thermal resistance (junction to case) 36.73 17.17 c/w ac test loads and waveforms figure 1. ac test loads and waveforms [4] data retention characteristics over the operating range parameter description conditions [4] min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v v in > v cc ? 0.3 v or v in < 0.3 v ?10ma t cdr [2] chip deselect to data retention time 0 ? ns t r [5] operation recovery time t rc ?ns figure 2. data retention waveform 90% 10% 3.0 v gnd 90% 10% all input pulses * capacitive load consists of all components of the test environment rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 50 1.5 v (b) (a) 3.3 v output 5 pf (c) r 317 r2 351 high z characteristics: 10 ns device 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc notes 2. tested initially and after any design or proce ss changes that may affect these parameters. 3. ac characteristics (except high z) are tested using the load conditions shown in figure 1 (a). high z characteristics are tested for all speeds using the test load shown in figure 1 (c). 4. no input may exceed v cc + 0.3 v. 5. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s.
cy7c1049dv33 document number: 38-05475 rev. *h page 6 of 14 ac switching characteristics over the operating range [6] parameter description -10 (industrial) unit min max read cycle t power [7] v cc (typical) to the first access 100 ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5ns t lzoe oe low to low z [8] 0 ? ns t hzoe oe high to high z [8, 9] ? 5ns t lzce ce low to low z [8] 3 ? ns t hzce ce high to high z [8, 9] ? 5ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 10 ns write cycle [10, 11] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7 ? ns t sd data setup to write end 5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3 ? ns t hzwe we low to high z [8, 9] ? 5ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30 pf load capacitance. 7. t power gives the minimum amount of time that the power supply must be at stable, typical v cc values until the first memory access is performed. 8. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of figure 1 on page 5 . transition is measured when the outputs enter a high impedance state. 10. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set up and hold timing must be referred to the leading edge of the signal that terminat es the write. 11. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1049dv33 document number: 38-05475 rev. *h page 7 of 14 switching waveforms figure 3. read cycle no. 1 [12, 13] figure 4. read cycle no. 2 (oe controlled) [13, 14] figure 5. write cycle no. 1 (we controlled, oe high during write) [15, 16] previous data valid data out valid t rc t aa t oha address data i/o 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data i/o v cc supply current t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 16 notes 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. 15. data i/o is high impedance if oe = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high impedance state.
cy7c1049dv33 document number: 38-05475 rev. *h page 8 of 14 figure 6. write cycle no. 2 (we controlled, oe low) [17] figure 7. write cycle no. 3 (ce controlled) [17, 19] switching waveforms (continued) data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 t wc data in valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o notes 17. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 18. during this period the i/os are in the output state and input signals must not be applied. 19. data i/o is high impedance if oe = v ih .
cy7c1049dv33 document number: 38-05475 rev. *h page 9 of 14 truth table ce oe we io 0 ?io 7 mode power h x x high z power down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 10 CY7C1049DV33-10VXI 51-85090 36-pin (400-mil) molded soj (pb-free) industrial cy7c1049dv33-10zsxi 51-85087 44-pin tsop ii (pb-free) contact your local cypress sales repres entative for availability of these parts. ordering code definitions temperature range: x = i i = industrial pb-free package type: xx = v or zs v = 36-pin (400-mil) molded soj zs = 44-pin tsop ii speed: xx = 10 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 9 = data width 8-bits 04 = 4-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 v33 - xx xx 7 04 9 d x x
cy7c1049dv33 document number: 38-05475 rev. *h page 10 of 14 package diagrams figure 8. 36-pin (400-mil) molded soj v36.4, (51-85090) 51-85090 *e
cy7c1049dv33 document number: 38-05475 rev. *h page 11 of 14 figure 9. 44-pin tsop z44-ii, (51-85087) package diagrams (continued) 51-85087 *c
cy7c1049dv33 document number: 38-05475 rev. *h page 12 of 14 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celcius mhz megahertz a microamperes s microseconds ma milliamperes mm millimeter ms milliseconds ns nanoseconds ohms % percent pf pico farad vvolts wwatts
cy7c1049dv33 document number: 38-05475 rev. *h page 13 of 14 document history page document title: cy7c1049dv33, 4-mbit (512 k 8) static ram document number: 38-05475 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance datasheet for c9 ipp *a 233729 see ecn syt 1.ac, dc parameters are mo dified as per eros (specification # 01-2165) 2.pb-free offering in the ordering information table *b 351096 see ecn pci changed from advance to preliminary removed 20 ns speed bin corrected dc voltage (min) value in maximum ratings section from - 0.5 to - 0.3v redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 100, 80, and 67 ma to 90, 80 and, 75 ma for 8, 10, and 12ns speed bins respectively i cc (ind?l): changed from 80 and 67 ma to 90 and 85 ma for 10 and 12ns speed bins respectively added v ih(max ) specification in note# 2 changed reference voltage level for measurement of high z parameters from 500 mv to 200 mv added data retention characteristics, waveform, and footnotes 11 and 12 changed package diagram name from 44-pin tsop ii z44 to 44-pin tsop ii zs44 changed part names from z to zs in the ordering information table added 8 ns parts in the ordering information table added pb-free ordering information shaded ordering information table *c 446328 see ecn nxr converted from preliminary to final removed -8 speed bin removed commercial operating range product information added automotive operating range product information updated thermal resistance table updated footnote #8 on high z parameter measurement replaced package name column with package diagram in the ordering infor- mation table *d 1274726 see ecn vkn/aesa corrected typo in the 44-pin tsop ii pinout *e 2899972 03/29/2010 aju updated package diagrams . *f 3059162 10/14/2010 pras added ordering code definitions . updated package diagrams . *g 3266084 05/28/2011 pras updated functional description (removed ?refer to the cypress application note an1064, sram system guidelines fo r best practice recommendations.?). added acronyms and units of measure . updated in new template. *h 3440302 11/16/2011 tava removed automotive part information from the datasheet. updated read and write waveforms.
document number: 38-05475 rev. *h revised november 16, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1049dv33 ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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